This invention relates to the physical structure of lightly doped drain field effect transistors (LDD transistors), and methods of fabricating same, such that the transistor has a large saturation current with small tolerances.
In the semiconductor industry, many attempts have been made to fabricate field effect transistors with a reduced size in order that more and more circuitry can be placed on a single integrated circuit chip. As a result of those efforts, LDD transistors have been developed. Various processes for forming LDD transistors, and the resulting structures, are described in the following technical papers: (1) "Experimental Technology and Characterization of Self-Aligned 0.1 um Gate Length Low-Temperature Operation NMOS Devices" by Sai-Halasz et al published in the IEDM of 1987 at pages 397-400; (2) "Si.sub.3 N.sub.4 /SiO.sub.2 Spacer Induced High Reliability in LDDMOSFET and Its Simple Degradation Model" by T. Mizumo et al published in the IEDM of 1988 at pages 234-235; (3) "Poly-Gate Sidewall Oxidation Induced Submicrometer MOSFET Degradation" by Pfiester et al published in the IEEE Electron Device Letters, Volume 10, Number 8, August 1989 at pages 367-369; (4) "Submicrometer Salicide CMOS Devices with Self-Aligned Shallow/Deep Junctions" by Lu et al published in the IEEE Electron Device Letters, Volume 10, Number 11, November 1990 at pages 487-489; and (5) "A Poly-Framed LDD Sub-Half-Micrometer CMOS Technology" by Pfiester et al published in the IEEE Electron Device Letters, Volume 11, Number 11, November 1990 at pages 529-531.
In all of the above papers, a field effect transistor is described which has source and drain regions that are lightly doped adjacent to the transistor gate and are heavily doped at a space of several hundred angstroms from the gate. Such an LDD structure is desirable in submicron transistors because it reduces the electric field at the source and drain directly below the edges of the gate electrode; and, that in turn reduces hot carrier effects which produce long term shifts in the transistor's threshold voltage.
To change the doping from light to heavy in the source and drain regions, small submicron spacers are formed on the sidewalls of the gate electrode. These spacers are used as a mask, when the heavily doped portion of the source and drain is implanted, which keeps the heavy doping away from the gate electrode. However, in all of the process variations which the above referenced papers disclose, the present inventors have determined that a certain technical deficiency exists with the manner in which the spacer is fabricated.
Due to this deficiency, the transistor's saturation current is lowered; and, the range over which the transistor's saturation current will vary is increased. By definition, when the current through a field effect transistor is below its saturation level, an increase in the source-drain voltage with the gate voltage held constant will produce a linearly proportional increase in current; whereas when the saturation level is exceeded, the current through the field effect transistor remains essentially constant. Thus, a saturation current which is consistently large is desirable since it expands the voltage range over which the transistor can operate as a linear amplifier and increases the transistor's maximum output current or drive current.
Accordingly, a primary object of the invention is to provide an improved process for fabricating LDD field effect transistors in which the above described problems are overcome.